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Features
* Third Generation Programmable Logic Structure
- Easily Achieves Gate Utilization Factors of 80 Percent
* Increased Logic Flexibility
- 86 Inputs and 72 Sum Terms
* Flexible Output Macrocell * * * * * * *
- 48 Flip-Flops - 2 per Macrocell - 3 Sum Terms - Can Be OR'ed and Shared High-Speed Low-Power -- Less than 0.5 mA Typical (ATV2500L) Multiple Feedback Paths Provide for Buried State Machines and I/O Bus Compatibility Asynchronous Clocks and Resets - Multiple Synchronous Presets - One per Four or Eight Flip-Flops Proven and Reliable High Speed CMOS EPROM Process - 2000V ESD Protection - 200 mA Latchup Immunity Reprogrammable - Tested 100% for Programmability 40-pin Dual-In-line and 44-Lead Surface Mount Packages
High-Density UV-Erasable Programmable Logic Device ATV2500H ATV2500L
Block Diagram
Description
The ATV2500H/L is the most powerful programmable logic device available in a 40pin package. Increased product terms, sum terms, and flip-flops translate into many more usable gates. High gate utilization is easily obtainable. The ATV2500H/L is organized around a global bus. All pin and feedback terms are always available to every logic cell. Each of the 38 logic pins and their complements are array inputs, as well as the true and false outputs of each of the 48 flip-flops. (continued)
Pin Configurations
Pin Name IN I/O I/O, 0,2,4.. I/O, 1,3,5.. * VCC Function Logic Inputs Bidirectional Buffers "Even" I/O Buffers "Odd" I/O Buffers No Internal Connection +5V Supply
IN IN IN I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 VCC I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 IN IN IN IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
DIP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 IN IN IN IN I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 GND I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 IN IN IN
PLCC/LCC
I/O1 I/O0 * IN IN IN IN IN IN IN I/O06
* = No Connect
Rev. 0025E-05/98
I/O12 IN IN IN IN IN IN IN * I/O18 I/O19
18 19 20 21 22 23 24 25 26 27 28
I/O2 I/O3 I/O4 I/O5 VCC VCC I/O17 I/O16 I/O15 I/O14 I/O13
7 8 9 10 11 12 13 14 15 16 17
6 5 4 3 2 1 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30 29
I/O7 I/O8 I/O9 I/O10 I/O11 GND GND I/O23 I/O22 I/O21 I/O20
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There are 416 product terms available. Four product terms are input to each sum term. The three sum terms per logic cell can be combined to provide up to twelve product terms, combinatorial and registered. Independent of output configuration, the two flip-flops are always usable, and always have at least four product term inputs.
Product terms are available providing asynchronous resets, flip-flop clocks, and output enables. One reset and one clock term are provided per flip-flop, with one enable term per output. Eight product terms provide local synchronous presets, divided up into banks of four and eight flipflops. Register preload and buried register observability simplify testing. The device has an internal power up clear function.
Functional Logic Diagram ATV2500H/L
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ATV2500H/L
ATV2500H/L
Functional Logic Diagram Description
The ATV2500H/L Functional Logic Diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the global bus. The ATV2500H/L is a straightforward and uniform PLD. The twenty-four macrocells are numbered 0 through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous reset and clock per flip-flop, and an output enable. The top twelve product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing Preset 7. The fourteen dedicated inputs and their complements use the numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right) flip-flop Q2 true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Absolute Maximum Ratings*
Temperature Under Bias ............................... -55C to + 125C Storage Temperature .................................... -65C to + 150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) Integrated UV Erase Dose.............................. 7258 W.sec/cm2 1. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns.
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Output Logic, Registered
Output Logic, Combinatorial
These diagrams show equivalent logic functions, not necessarily the actual circuit implementation.
Terms In S2 0 0 Note: S1 0 1 S0 0 0 D1 8 12 D2 4 4(1) Output Configuration Registered (Q1) Registered (Q1) S2 1 1 1 Note: S3 0 1 Output Configuration Active Low Active High S3 0 1 S1 0 0 1 S0 0 1 0
Terms In D1 4
(1)
D2 4 4 4
(1)
Output Configuration Combinatorial (8 Terms) Combinatorial (4 Terms) Combinatorial (12 Terms)
4 4
(1)
1. These 4 terms are shared with D1.
1. These 4 terms are shared with D1. Output Configuration Active Low Active High
DC and AC Operating
ATV2500H-25 Operating Temperature (Case) VCC Power Supply Com. Ind. Mil. 0C - 70C -40C - 85C -55C - 125C 5V 10% ATV2500H/L-30 0C - 70C -40C - 85C -55C - 125C 5V 10% ATV2500H/L-35 0C - 70C -40C - 85C -55C - 125C 5V 10%
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ATV2500H/L
ATV2500H/L
DC Characteristics
Symbol ILI ILO ICC Parameter Input Load Current Output Leakage Current Power Supply Current Condition VIN = -0.1V to VCC + 1V VOUT = -0.1V to VCC + 0.1V VCC = MAX, VIN = GND or VCC Outputs Open ATV2500L Com. Ind.,Mil. ATV2500H Com. Ind.,Mil. IOS(1) VIL VIH VOL VOH Note: Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VIN = VIH or VIL, IOL = 8 mA Com,Ind; 6 mA Mil. IOH = -100 A IOH = -4.0 mA VCC - 0.3 2.4 VOUT = 0.5V -0.6 2.0 0.5 0.5 80 80 Min Typ Max 10 10 5 10 160 180 -120 0.8 VCC + 0.75 0.5 Units A A mA mA mA mA mA V V V V V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. This parameter is only sampled and is not 100% tested. See Absolute Maximum Ratings.
Pin Capacitance (f = MHz, T = 25C)(1)
Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = OV VOUT = OV
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
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AC Waveforms(1)
Note:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics for the ATV2500L
ATV2500L-30 Symbol tPD tEA tER tCO tCF tSI1 tSI2 tSF tH1 tH2 tW tP FMAX tAW tAR tAP Note: Parameter Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time, Output Register Input Setup Time, Buried Register(1) Feedback Setup Time Hold Time, Output Register Hold Time, Buried Register Clock Width Clock Period Maximum Frequency (1/tP) Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset 18 18 30
(1)
ATV2500L-35 Min Max 35 35 35 5 15 22 22 15 15 5 17 35 35 20 Units ns ns ns ns ns ns ns ns ns ns ns ns 28 20 20 35 MHz ns ns ns
Min
Max 30 30 30
5 10 20 20 10 10 5 15 30
30 20
33
1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial.
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ATV2500H/L
ATV2500H/L
AC Characteristics for the ATV2500H
ATV2500H-25 Symbol tPD tEA tER tCO tCF tSI1 tSI2 tSF tH1 tW tP FMAX tAW tAR tAP Note: Parameter Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time, Output Register Input Setup Time, Buried Register(1) Feedback Setup Time Hold Time Clock Width Clock Period Maximum Frequency (1/tP) Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset 15 15 25 10 10 10 5 7 5 10 25 40 18 18 30 Min Max 25 25 25 25 18 12 12 12 5 10 5 12 30 33 20 20 35 ATV2500H-30 Min Max 30 30 30 30 20 15 15 15 5 15 5 15 35 28 ATV2500H-35 Min Max 35 35 35 35 20 Units ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns
1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial.
Input Test Waveforms and Measurement Levels
Output Test Loads
tR, tF < 5 ns (10% to 90%)
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Preload and Observability of Registered Outputs
The ATV2500H/L's registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the Odd I/O pins will force the appropriate register high; a VIL will force it low, independent of the polarity or other configuration bit settings. The preload state is entered by placing an 11V to 14V signal on pin 38 on the DIP and pin 42 on the SMP. When the clock term is pulsed high, (pin 21 on the DIP, pin 23 on the SMP) the data on the I/O pins is placed into the 12 registers chosen by the Q select and even/odd select pins. Register 2 observability mode is entered by placing an 11V to 14V signal on pin 2 (DIP or SMP). In this mode, the contents of the buried register bank will appear on the associated outputs when the OE control signals are active.
Level forced on Odd I/O pin during preload cycle. VIH VIL VIH VIL VIH VIL VIH VIL
Q Select pin state Low Low High High Low Low High High
Even/ Odd select Low Low Low Low High High High High
Even Q1 state after cycle High Low X X X X X X
Even Q2 state after cycle X X High Low X X X X
Odd Q1 state after cycle X X X X High Low X X
Odd Q2 state after cycle X X X X X X High Low
Power-Up Reset
The registers in the ATV2500H/L are designed to reset during power-up. At a point delayed slightly from VCC crossing 3.8V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock term high, 3. The signals from which the clock is derived must remain stable during tPR. 8
Parameter tPR
Description Power-Up Reset Time
Min
Typ 600
Max 1000
Units ns
ATV2500H/L
ATV2500H/L
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATV2500H/L fuse patterns. Once programmed, the outputs will read programmed during verify. The security fuse should be programmed last, as its effect is immediate. The security fuse also inhibits preload and Q2 observability. * Independent I/O Pin and Feedback Paths Each I/O pin on the ATV2500/H has a dedicated input path. Each of the 48 registers has individual feedback terms into the array. This feature, combined with individual product terms for each I/O's output enable, facilitates designs using bi-directional I/O buses. * Three Sum Terms per Macrocell The ATV2500H/L macrocell can be configured with one SUM term feeding the output, and still have two SUM terms feeding the flip-flops. This is the simplest method for interfacing with an I/O bus, and no flip-flops need be sacrificed. * Combinable Sum Terms Each output macrocell's three SUM terms can be combined in an OR gate before the output or the register. This provides up to twelve product terms per output or flip-flop. When the registered output configuration is chosen, eight terms are automatically available to D1. The four terms feeding D2 can also be shared with D1, giving it a total of twelve. In the combinatorial mode, four, eight, or twelve terms can feed the output, with the middle four still driving D1 and the bottom four still driving D2.
Atmel CMOS PLDs
Atmel's Erasable Programmable Logic Devices utilize an advanced 1.25-micron CMOS EPROM technology. This technology's state of the art features are the optimum combination for PLDs: * CMOS technology provides high speed, low power, and high noise immunity. * EPROM technology is the most cost effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability. * EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs. * Atmel's EPROM process has proven extremely reliable in the volume production of a full line of advanced EPROM memory products, from 64K to one-megabit devices.
Programming Software Support
Software which is capable of transforming Boolean equations, state machine descriptions and truth tables into JEDEC files for the ATV2500H/L is currently available from several PLD software vendors. Please refer to the Programmable Logic Development Tools section for a complete listing of the PLD software support.
Using the ATV2500H/L's Many Advanced Features
The ATV2500H/L's flexibility puts more usable gates in 40 pins than other PLDs. Some of the ATV2500H/L's key features are: * Asynchronous Clocks Each of the flip-flops in the ATV2500H/L has a dedicated product term driving the clock. The user is no longer constrained to using one clock for all the registers. Buried state machines, counters, and registers can all coexist in one device, while running on separate clocks. The ATV2500H/L clock period matches that of similar synchronous devices. * A Total of 48 Registers The ATV2500H/L provides two flip-flops for each output macrocell - a total of 48. Each register has its own clock and reset product terms, as well as its own sum term.
Erasure Characteristics
The entire memory array of an ATV2500H/L is erased after exposure to ultraviolet light at a wavelength of 2537 A. Complete erasure is assured after a minimum of twenty minutes exposure using 12,000 W/cm 2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of fifteen W*sec/cm2. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight.
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Note:
All normalized values referenced to maximum specification in AC characteristics section of datasheet.
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ATV2500H/L
ATV2500H/L
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Ordering Information
tPD (ns) tCO (ns) fMAX (MHz) Ordering Code ATV2500H-25DC ATV2500H-25JC ATV2500H-25KC ATV2500H-25LC ATV2500H-25PC ATV2500H-25DI ATV2500H-25JI ATV2500H-25KI ATV2500H-25LI ATV2500H-25PI ATV2500H-25DM ATV2500H-25KM ATV2500H-25LM ATV2500H-25DM/883 ATV2500H-25KM/883 ATV2500H-25LM/883 30 30 33 ATV2500H-30DC ATV2500H-30JC ATV2500H-30KC ATV2500H-30LC ATV2500H-30PC ATV2500H-30DI ATV2500H-30JI ATV2500H-30KI ATV2500H-30LI ATV2500H-30PI 35 35 28 ATV2500H-35DC ATV2500H-35JC ATV2500H-35KC ATV2500H-35LC ATV2500H-35PC ATV2500H-35DI ATV2500H-35JI ATV2500H-35KI ATV2500H-35LI ATV2500H-35PI 25 25 40 5962-91545 02M QA 5962-91545 02M XX 5962-91545 02M YX Package 40DW6 44J 44KW 44LW 40P6 40DW6 44J 44KW 44LW 40P6 40DW6 44KW 44LW 40DW6 44KW 44LW 40DW6 44J 44KW 44LW 40P6 40DW6 44J 44KW 44LW 40P6 40DW6 44J 44KW 44LW 40P6 40DW6 44J 44KW 44LW 40P6 40DW6 44LW 44KW Operation Range Commercial (0C to 70C)
25
25
40
Industrial (-40C to 85C)
Military (-55C to 125C) Military/883C (-55C to 125C) Class B, Fully Compliant Commercial (0C to 70C)
Industrial (-40C to 85C)
Commercial (0C to 70C)
Industrial (-40C to 85C)
Military/833C (-55C to 125C) Class B, Fully Compliant
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ATV2500H/L
ATV2500H/L
Ordering Information (Continued)
tPD (ns) 30 tCO (ns) 30 fMAX (MHz) 33 Ordering Code ATV2500L-30DC ATV2500L-30JC ATV2500L-30KC ATV2500L-30LC ATV2500L-30PC ATV2500L-30DI ATV2500L-30JI ATV2500L-30KI ATV2500L-30LI ATV2500L-30PI ATV2500L-30DM ATV2500L-30KM ATV2500L-30LM ATV2500L-30DM/883 ATV2500L-30KM/883 ATV2500L-30LM/883 35 35 28 ATV2500L-35DC ATV2500L-35JC ATV2500L-35KC ATV2500L-35LC ATV2500L-35PC ATV2500L-35DI ATV2500L-35JI ATV2500L-35KI ATV2500L-35LI ATV2500L-35PI 30 30 33 5962-91545 03M QA 5962-91545 03M XX 5962-91545 03M YX Package 40DW6 44J 44KW 44LW 40P6 40DW6 44J 44KW 44LW 40P6 40DW6 44KW 44LW 40DW6 44KW 44LW 40DW6 44J 44KW 44LW 40P6 40DW6 44J 44KW 44LW 40P6 40DW6 44LW 44KW Operation Range Commercial (0C to 70C)
Industrial (-40C to 85C)
Military (-55C to 125C) Military (-55C to 125C) Class B, Fully Compliant Commercial (0C to 70C)
Industrial (-40C to 85C)
Military/833C (-55C to 125C) Class B, Fully Compliant
Package Type 40DW6 44J 44KW 44LW 40P6 40-Lead, 0.600" Wide Windowed, Ceramic Dual In-line Package (Cerdip) 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 44-Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) 44-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 40-Lead, 0.600" Wide Plastic Dual In-line Package OTP (PDIP)
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Packaging Information
40DW6, 40-Lead, 0.600" Wide Windowed, Ceramic Dual In-line Package (Cerdip) Dimensions in Inches and (Millimeters)
MIL-STD-1835 D-5 CONFIG A
.045(1.14) X 45 PIN NO. 1 IDENTIFY .045(1.14) X 30 - 45
44J, 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) Dimensions in Inches and (Millimeters)
.012(.305) .008(.203)
.656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4)
.630(16.0) .590(15.0) .021(.533) .013(.330)
.050(1.27) TYP .500(12.7) REF SQ
.043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19)
.022(.559) X 45 MAX (3X)
44KW, 44-Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) Dimensions in Inches and (Millimeters)
MIL-STD-1835 C-J1
.035(.889) X 45 .045(1.14) X 45 .010(.254) .006(.152)
44LW, 44-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)
MIL-STD-1835 C-5
.032(.813) .026(.660)
.665(16.9) SQ .645(16.4) .695(17.7) SQ .685(17.4)
.630(16.0) .590(15.0) .021(.533) .017(.432)
.050(1.27) TYP .500(12.7) REF SQ
.045(1.14) .035(.889) .120(3.05) .090(2.29) .180(4.57) .156(3.96)
.025(.635) RADIUS MAX (3X)
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ATV2500H/L
ATV2500H/L
Packaging Information
40P6, 40-Lead, 0.600" Wide Plastic Dual Inline Package OTP (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AC
2.07(52.6) 2.04(51.8)
PIN 1
.566(14.4) .530(13.5)
1.900(48.26) REF .220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18) .110(2.79) .090(2.29) .065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 REF 15 .690(17.5) .610(15.5)
.090(2.29) MAX .005(.127) MIN
.065(1.65) .015(.381) .022(.559) .014(.356)
.012(.305) .008(.203)
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